The present invention relates to a semiconductor package, and more particularly, to a method of manufacturing a wafer level stack package in which semiconductor chips are stacked at a wafer level and connected to one another using via patterns.
Semiconductor devices were used for military purposes or computers in the earlier days. However, as society continues to evolve in response to the development of the Internet and other communication technologies, the application range of semiconductor devices has gradually increased. As a result, semiconductor devices are currently utilized in most electrical appliances, ranging from mobile products, including mobile phones and personal digital assistants (“PDA”), to traditional electrical home appliances, including televisions, audio systems, and even home boilers. In their application to various product groups, semiconductor devices must be capable of performing various functions. In particular, mobile products, such as mobile phones, increasingly demand high-speed, miniaturized semiconductors capable of multiple functionalities.
However, the complexity of circuits, ill-equipped manufacturing facilities, and increased processing costs have made it difficult to adapt the semiconductor manufacturing process to the demands of the afore-described technologies. As a result of these difficulties, the stack package has drawn considerable attention. In a stack package, uniform or different types of semiconductor chips are vertically stacked at the chip level or wafer level and electrically connected to one another through the via patterns formed on the respective chips, thereby producing one package.
Because the chips are vertically stacked in a stack package, unlike the existing single chip package, it is possible to manufacture a stack package with increased storage capacity by stacking uniform-type or size chips. It is also possible to manufacture a stack package capable of performing multiple functions by stacking different types of chips with information storage functions and logical operation functions. By vertically stacking chips in the aforementioned manner, it is therefore possible to create a miniaturized, multi-functional semiconductor product. Moreover, since the manufacture of stack packages merely requires existing semiconductor chips to be stacked in a combined manner and does not necessitate new equipment, the development time is shortened while the value of the end product is increased. Most importantly, the demands of various customers can be met simultaneously, and a new market can be developed by the application of the described technology to various product groups.
FIG. 1 is a cross-sectional view illustrating a conventional stack package. Referring to FIG. 1, uniform-size chips 110, 120, 130 and 140, are respectively formed with via patterns 112, 122, 132 and 142, are stacked on a substrate 100 through use of an adhesive 150. The upper surface of the substrate 100, including the chips 110, 120, 130 and 140, is molded by a molding material 160, and solder balls 170 are attached to the lower surface of the substrate 100.
The via patterns 112, 122, 132 and 142 used to electrically connect the stacked chips are formed as described below. FIGS. 2A through 2F are cross-sectional views illustrating the process steps for explaining a conventional method of forming via patterns. The respective drawings illustrate only via pattern forming regions.
Referring to FIG. 2A, a first photoresist pattern 202, which exposes the via pattern forming regions, is formed on the front side of a wafer 200 through a photolithography process.
Referring to FIG. 2B, the exposed regions of the wafer 200 are etched using the first photoresist pattern 202 as an etch barrier, thereby defining trenches T. At this time, the trenches T are defined to a depth so as to not pass through the wafer 200. Then, the first photoresist pattern 202 used as the etch barrier is removed.
Referring to FIG. 2C, an insulation layer 204 and a seed layer 206 are sequentially formed on the front side of the wafer 200 including the surfaces of the trenches T. A second photo resist pattern 208, which exposes the via pattern forming regions, is formed on the seed layer 206. A metal layer, such as a Cu layer, is formed on the exposed portions of the seed layer 206 using an appropriate method, such as electro plating, thereby forming via patterns 212 that fill the trenches T. While it is described that the via patterns 212 are formed through an electro plating method, they can also be formed using other methods, such as a damascene process.
Referring to FIG. 2D, the second photoresist pattern 208 is removed. The portions of the seed layer 206 exposed by the removal of the second photoresist pattern 208 are subsequently removed in the same manner.
Referring to FIG. 2E, in order to improve workability in a subsequent back grinding process, that is, in order to prevent the wafer 200 from being damaged during a back grinding process, a protective layer 214 made of glass is formed on the front side of the wafer 200 which is formed with the via patterns 212.
Referring to FIG. 2F, the back side of the wafer 200 is ground such that the lower ends of the via patterns 212 are exposed, and the back side of the ground wafer 200 is wet or dry etched to expose a portion of the lower ends of the via patterns 212. Then, the protective layer 214 is removed. Thereupon, the wafer level chips are divided into a chip level through a sawing process.
In a stack package in which semiconductor chips are connected through the via patterns formed as described above, the difficulties of securing space for the formation of bonding wires is eliminated, thereby allowing the size of the package to be decreased and the mounting density to be increased. Also, in a stack package in which semiconductor chips are connected through the via patterns, use of the via patterns as the shortest interconnection routes allows for excellent electrical characteristics.
However, in the above-described conventional stack package, since stacking is implemented at the chip level, as compared to a type in which stacking is implemented at the wafer level, the need to repeatedly conduct the process for each package increases the processing time and manufacturing costs.
Meanwhile, in a stack package using via patterns, if the wafer level structure is sawed into chip level structures after stacking is implemented at the wafer level, the number of processes, the processing time and the manufacturing costs can be decreased. Nevertheless, when stacking is implemented at the wafer level according to the conventional art, a serious problem is caused in that handling of a thin and wide wafer is likely to cause stresses and cracks in the wafer, and the wafer is likely to be broken. Hence, in the conventional art, difficulties exist in implementing the stacking at the wafer level.